Regviz

Silicon Labs /SiM3_NRND /SIM3C164_B /SARADC_0 /FIFOSTATUS

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as FIFOSTATUS

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Silicon Labs/SiM3_NRND/SIM3C167_B/SARADC_0/FIFOSTATUS#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FIFOLVL0 (LOWER)DPSTS 0 (NOT_SET)DRDYF

DPSTS=LOWER, DRDYF=NOT_SET

Description

FIFO Status

Fields

FIFOLVL

FIFO Level.
DPSTS

Data Packing Status.

0 (LOWER): The next ADC conversion will be written to the lower half-word.

1 (UPPER): The next ADC conversion will be written to the upper half-word.
DRDYF

Data Ready Flag.

0 (NOT_SET): New data is not produced yet.

1 (SET): New data is ready.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data